As semiconductor line widths decrease, designers and programmers are configuring the devices to run at faster speeds. In addition to the demand for higher speed devices, demands also exist for device performance with higher levels of signal accuracy. One example of electronic devices where signal accuracy is of great importance is devices that communicate wirelessly.
One tool used by designers to improve the accuracy of a signal is a phase locked loop (PLL). A PLL is an electronic control system that generates a signal that is locked to the phase (and frequency) of an input or “reference” signal. PLLs are widely used in radio, telecommunications and computers to generate stable frequency signals, or to recover a signal from a noisy communication channel. A PLL includes specific circuit components to adjust the control voltage of a voltage controllable oscillator until its output phase is identical to that of the reference signal.
FIG. 1 illustrates a sample PLL 100. Here, the reference signal 102 is input to the reference divider 104. The reference divider 104 reduces the clock rate of the reference signal to a rate that the other components can process. After dividing the frequency of the reference signal (if needed), the reference divider 104, passes the signal to the phase detector 106.
The phase detector 106 is the control element of the PLL 100. The phase detector 106 compares the phases of its two input clocks (in this example, the reference signal supplied by the reference divider 104 and the output of the voltage controllable oscillator feedback divider 112) and provides a corrective signal that is filtered which controls the oscillator to force the phase between the two compared clock signals to zero. In this example, the phase detector 106 provides a control signal to the loop filter 108.
The optional loop filter 108 receives the control signal from the phase detector 106 and creates a low pass filtered version of the phase detector output (VLF). For a voltage controlled oscillator (VCO) with a positive transfer function slope, the loop filter output voltage increases if the oscillator should produce a higher frequency signal, and conversely, is lowered if the oscillator should produce a lower frequency signal to match the two clock phases. The voltage controlled oscillator output is provided to an optional feedback divider 112. In FIG. 100, the feedback divider splits the output of the controlled oscillator 110 into two signals; one output provides the feedback input to the phase detector 106 for further comparison; the second output signal is an output signal 114.
The PLL described in FIG. 1 is a typical approach to producing phase locked signals. When implemented in an integrated circuit, PLL circuit performance can vary greatly over different silicon processes, voltage and temperature. A slight temperature change can change the value of the circuit components (e.g., the loop filter) or functionality of other PLL elements. Under some combinations of silicon process, supply voltage and temperature, there are occasions when the loop filter cannot produce a voltage signal that will result in the controlled oscillator producing a signal with the same phase as the reference signal. To avoid this undesirable condition, a PLL trimming method that calibrates components of the PLL, in particular the controlled oscillator, is often employed.